
use crate::metadata::ir::*;
pub(crate) static REGISTERS: IR = IR {
    blocks: &[Block {
        name: "Adc",
        extends: None,
        description: Some("Analog-to-Digital Converter"),
        items: &[
            BlockItem {
                name: "isr",
                description: Some("interrupt and status register"),
                array: None,
                byte_offset: 0x0,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Isr"),
                }),
            },
            BlockItem {
                name: "ier",
                description: Some("interrupt enable register"),
                array: None,
                byte_offset: 0x4,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Ier"),
                }),
            },
            BlockItem {
                name: "cr",
                description: Some("control register"),
                array: None,
                byte_offset: 0x8,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Cr"),
                }),
            },
            BlockItem {
                name: "cfgr",
                description: Some("configuration register"),
                array: None,
                byte_offset: 0xc,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Cfgr"),
                }),
            },
            BlockItem {
                name: "smpr1",
                description: Some("sample time register 1"),
                array: None,
                byte_offset: 0x14,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Smpr1"),
                }),
            },
            BlockItem {
                name: "smpr2",
                description: Some("sample time register 2"),
                array: None,
                byte_offset: 0x18,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Smpr2"),
                }),
            },
            BlockItem {
                name: "tr1",
                description: Some("watchdog threshold register 1"),
                array: None,
                byte_offset: 0x20,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Tr1"),
                }),
            },
            BlockItem {
                name: "tr2",
                description: Some("watchdog threshold register"),
                array: None,
                byte_offset: 0x24,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Tr2"),
                }),
            },
            BlockItem {
                name: "tr3",
                description: Some("watchdog threshold register 3"),
                array: None,
                byte_offset: 0x28,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Tr3"),
                }),
            },
            BlockItem {
                name: "sqr1",
                description: Some("regular sequence register 1"),
                array: None,
                byte_offset: 0x30,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Sqr1"),
                }),
            },
            BlockItem {
                name: "sqr2",
                description: Some("regular sequence register 2"),
                array: None,
                byte_offset: 0x34,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Sqr2"),
                }),
            },
            BlockItem {
                name: "sqr3",
                description: Some("regular sequence register 3"),
                array: None,
                byte_offset: 0x38,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Sqr3"),
                }),
            },
            BlockItem {
                name: "sqr4",
                description: Some("regular sequence register 4"),
                array: None,
                byte_offset: 0x3c,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Sqr4"),
                }),
            },
            BlockItem {
                name: "dr",
                description: Some("regular Data Register"),
                array: None,
                byte_offset: 0x40,
                inner: BlockItemInner::Register(Register {
                    access: Access::Read,
                    bit_size: 32,
                    fieldset: Some("Dr"),
                }),
            },
            BlockItem {
                name: "jsqr",
                description: Some("injected sequence register"),
                array: None,
                byte_offset: 0x4c,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Jsqr"),
                }),
            },
            BlockItem {
                name: "ofr",
                description: Some("offset register X"),
                array: Some(Array::Regular(RegularArray { len: 4, stride: 4 })),
                byte_offset: 0x60,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Ofr"),
                }),
            },
            BlockItem {
                name: "jdr",
                description: Some("injected data register X"),
                array: Some(Array::Regular(RegularArray { len: 4, stride: 4 })),
                byte_offset: 0x80,
                inner: BlockItemInner::Register(Register {
                    access: Access::Read,
                    bit_size: 32,
                    fieldset: Some("Jdr"),
                }),
            },
            BlockItem {
                name: "awdcr",
                description: Some("Analog Watchdog X Configuration\r Register"),
                array: Some(Array::Regular(RegularArray { len: 2, stride: 4 })),
                byte_offset: 0xa0,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Awdcr"),
                }),
            },
            BlockItem {
                name: "difsel",
                description: Some("Differential Mode Selection Register\r 2"),
                array: None,
                byte_offset: 0xb0,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Difsel"),
                }),
            },
            BlockItem {
                name: "calfact",
                description: Some("Calibration Factors"),
                array: None,
                byte_offset: 0xb4,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Calfact"),
                }),
            },
        ],
    }],
    fieldsets: &[
        FieldSet {
            name: "Awdcr",
            extends: None,
            description: Some("Analog Watchdog 2 Configuration\r Register"),
            bit_size: 32,
            fields: &[Field {
                name: "awd2ch0",
                description: Some("AWD2CH"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                bit_size: 1,
                array: Some(Array::Regular(RegularArray { len: 17, stride: 1 })),
                enumm: None,
            }],
        },
        FieldSet {
            name: "Calfact",
            extends: None,
            description: Some("Calibration Factors"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "calfact_s",
                    description: Some("CALFACT_S"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 7,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "calfact_d",
                    description: Some("CALFACT_D"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 7,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Cfgr",
            extends: None,
            description: Some("configuration register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "dmaen",
                    description: Some("Direct memory access enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dmacfg",
                    description: Some("Direct memory access configuration"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Dmacfg"),
                },
                Field {
                    name: "res",
                    description: Some("Data resolution"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Res"),
                },
                Field {
                    name: "align",
                    description: Some("Data alignment"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Align"),
                },
                Field {
                    name: "extsel",
                    description: Some("External trigger selection for regular group"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 4,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exten",
                    description: Some("External trigger enable and polarity selection for regular channels"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Exten"),
                },
                Field {
                    name: "ovrmod",
                    description: Some("Overrun Mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cont",
                    description: Some("Continuous conversion"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "autdly",
                    description: Some("Delayed conversion mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "discen",
                    description: Some("Discontinuous mode for regular channels"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "discnum",
                    description: Some("Discontinuous mode channel count"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 3,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jdiscen",
                    description: Some("Discontinuous mode on injected channels"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jqm",
                    description: Some("JSQR queue mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Jqm"),
                },
                Field {
                    name: "awd1sgl",
                    description: Some("Enable the watchdog 1 on a single channel or on all channels"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Awd1sgl"),
                },
                Field {
                    name: "awd1en",
                    description: Some("Analog watchdog 1 enable on regular channels"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jawd1en",
                    description: Some("Analog watchdog 1 enable on injected channels"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jauto",
                    description: Some("Automatic injected group conversion"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "awd1ch",
                    description: Some("Analog watchdog 1 channel selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
                    bit_size: 5,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Cr",
            extends: None,
            description: Some("control register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "aden",
                    description: Some("ADC enable control"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "addis",
                    description: Some("ADC disable command"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "adstart",
                    description: Some("ADC start of regular conversion"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jadstart",
                    description: Some("ADC start of injected conversion"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "adstp",
                    description: Some("ADC stop of regular conversion command"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jadstp",
                    description: Some("ADC stop of injected conversion command"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "advregen",
                    description: Some("ADC voltage regulator enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Advregen"),
                },
                Field {
                    name: "adcaldif",
                    description: Some("Differential mode for calibration"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "adcal",
                    description: Some("ADC calibration"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Difsel",
            extends: None,
            description: Some("Differential Mode Selection Register\r 2"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "difsel_10",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_11",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_12",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_13",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_14",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_15",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_16",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_17",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_18",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_19",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_110",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_111",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_112",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_113",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_114",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_115",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_116",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
                Field {
                    name: "difsel_117",
                    description: Some("Differential mode for channels 15 to\r 1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Difsel10"),
                },
            ],
        },
        FieldSet {
            name: "Dr",
            extends: None,
            description: Some("regular Data Register"),
            bit_size: 32,
            fields: &[Field {
                name: "rdata",
                description: Some("Regular data"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 16,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Ier",
            extends: None,
            description: Some("interrupt enable register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "adrdyie",
                    description: Some("ADC ready interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "eosmpie",
                    description: Some("End of sampling flag interrupt enable for regular conversions"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "eocie",
                    description: Some("End of regular conversion interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "eosie",
                    description: Some("End of regular sequence of conversions interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ovrie",
                    description: Some("Overrun interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jeocie",
                    description: Some("End of injected conversion interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jeosie",
                    description: Some("End of injected sequence of conversions interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "awdie",
                    description: Some("Analog watchdog X interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
                    bit_size: 1,
                    array: Some(Array::Regular(RegularArray { len: 3, stride: 1 })),
                    enumm: None,
                },
                Field {
                    name: "jqovfie",
                    description: Some("Injected context queue overflow interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Isr",
            extends: None,
            description: Some("interrupt and status register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "adrdy",
                    description: Some("ADC Ready"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "eosmp",
                    description: Some("End of sampling flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "eoc",
                    description: Some("End of conversion flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "eos",
                    description: Some("End of regular sequence flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ovr",
                    description: Some("ADC overrun"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jeoc",
                    description: Some("Injected channel end of conversion flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jeos",
                    description: Some("Injected channel end of sequence flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "awd",
                    description: Some("Analog watchdog flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
                    bit_size: 1,
                    array: Some(Array::Regular(RegularArray { len: 3, stride: 1 })),
                    enumm: None,
                },
                Field {
                    name: "jqovf",
                    description: Some("Injected context queue overflow"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Jdr",
            extends: None,
            description: Some("injected data register 1"),
            bit_size: 32,
            fields: &[Field {
                name: "jdata",
                description: Some("Injected data"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 16,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Jsqr",
            extends: None,
            description: Some("injected sequence register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "jl",
                    description: Some("Injected channel sequence length"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 2,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jextsel",
                    description: Some("External Trigger Selection for injected group"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 4,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "jexten",
                    description: Some("External Trigger Enable and Polarity Selection for injected channels"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Exten"),
                },
                Field {
                    name: "jsq",
                    description: Some("X conversion in the injected sequence"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 5,
                    array: Some(Array::Regular(RegularArray { len: 4, stride: 6 })),
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Ofr",
            extends: None,
            description: Some("offset register 1"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "offset",
                    description: Some("Data offset y for the channel programmed into bits OFFSETy_CH"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 12,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ch",
                    description: Some("Data offset y for the channel programmed into bits OFFSETy_CH"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
                    bit_size: 5,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "en",
                    description: Some("Offset y Enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Smpr1",
            extends: None,
            description: Some("sample time register 1"),
            bit_size: 32,
            fields: &[Field {
                name: "smp",
                description: Some("Channel x sampling time selection"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                bit_size: 3,
                array: Some(Array::Regular(RegularArray { len: 9, stride: 3 })),
                enumm: Some("SampleTime"),
            }],
        },
        FieldSet {
            name: "Smpr2",
            extends: None,
            description: Some("sample time register 2"),
            bit_size: 32,
            fields: &[Field {
                name: "smp",
                description: Some("Channel x sampling time selection"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 3,
                array: Some(Array::Regular(RegularArray { len: 9, stride: 3 })),
                enumm: Some("SampleTime"),
            }],
        },
        FieldSet {
            name: "Sqr1",
            extends: None,
            description: Some("regular sequence register 1"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "l",
                    description: Some("Regular channel sequence length"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 4,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "sq",
                    description: Some("X conversion in regular sequence"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 5,
                    array: Some(Array::Regular(RegularArray { len: 4, stride: 6 })),
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Sqr2",
            extends: None,
            description: Some("regular sequence register 2"),
            bit_size: 32,
            fields: &[Field {
                name: "sq",
                description: Some("X conversion in regular sequence"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 5,
                array: Some(Array::Regular(RegularArray { len: 5, stride: 6 })),
                enumm: None,
            }],
        },
        FieldSet {
            name: "Sqr3",
            extends: None,
            description: Some("regular sequence register 3"),
            bit_size: 32,
            fields: &[Field {
                name: "sq",
                description: Some("X conversion in regular sequence"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 5,
                array: Some(Array::Regular(RegularArray { len: 5, stride: 6 })),
                enumm: None,
            }],
        },
        FieldSet {
            name: "Sqr4",
            extends: None,
            description: Some("regular sequence register 4"),
            bit_size: 32,
            fields: &[Field {
                name: "sq",
                description: Some("X conversion in regular sequence"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 5,
                array: Some(Array::Regular(RegularArray { len: 2, stride: 6 })),
                enumm: None,
            }],
        },
        FieldSet {
            name: "Tr1",
            extends: None,
            description: Some("watchdog threshold register 1"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "lt1",
                    description: Some("LT1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 12,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ht1",
                    description: Some("HT1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 12,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Tr2",
            extends: None,
            description: Some("watchdog threshold register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "lt2",
                    description: Some("LT2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 8,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ht2",
                    description: Some("HT2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 8,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Tr3",
            extends: None,
            description: Some("watchdog threshold register 3"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "lt3",
                    description: Some("LT3"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 8,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ht3",
                    description: Some("HT3"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 8,
                    array: None,
                    enumm: None,
                },
            ],
        },
    ],
    enums: &[
        Enum {
            name: "Advregen",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "INTERMEDIATE",
                    description: Some(
                        "Intermediate state required when moving the ADC voltage regulator between states",
                    ),
                    value: 0,
                },
                EnumVariant {
                    name: "ENABLED",
                    description: Some("ADC voltage regulator enabled"),
                    value: 1,
                },
                EnumVariant {
                    name: "DISABLED",
                    description: Some("ADC voltage regulator disabled"),
                    value: 2,
                },
            ],
        },
        Enum {
            name: "Align",
            description: None,
            bit_size: 1,
            variants: &[
                EnumVariant {
                    name: "RIGHT",
                    description: Some("Right alignment"),
                    value: 0,
                },
                EnumVariant {
                    name: "LEFT",
                    description: Some("Left alignment"),
                    value: 1,
                },
            ],
        },
        Enum {
            name: "Awd1sgl",
            description: None,
            bit_size: 1,
            variants: &[
                EnumVariant {
                    name: "ALL",
                    description: Some("Analog watchdog 1 enabled on all channels"),
                    value: 0,
                },
                EnumVariant {
                    name: "SINGLE",
                    description: Some("Analog watchdog 1 enabled on single channel selected in AWD1CH"),
                    value: 1,
                },
            ],
        },
        Enum {
            name: "Difsel10",
            description: None,
            bit_size: 1,
            variants: &[
                EnumVariant {
                    name: "SINGLE_ENDED",
                    description: Some("Input channel is configured in single-ended mode"),
                    value: 0,
                },
                EnumVariant {
                    name: "DIFFERENTIAL",
                    description: Some("Input channel is configured in differential mode"),
                    value: 1,
                },
            ],
        },
        Enum {
            name: "Dmacfg",
            description: None,
            bit_size: 1,
            variants: &[
                EnumVariant {
                    name: "ONE_SHOT",
                    description: Some("DMA One Shot mode selected"),
                    value: 0,
                },
                EnumVariant {
                    name: "CIRCULAR",
                    description: Some("DMA Circular mode selected"),
                    value: 1,
                },
            ],
        },
        Enum {
            name: "Exten",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "DISABLED",
                    description: Some("Trigger detection disabled"),
                    value: 0,
                },
                EnumVariant {
                    name: "RISING_EDGE",
                    description: Some("Trigger detection on the rising edge"),
                    value: 1,
                },
                EnumVariant {
                    name: "FALLING_EDGE",
                    description: Some("Trigger detection on the falling edge"),
                    value: 2,
                },
                EnumVariant {
                    name: "BOTH_EDGES",
                    description: Some("Trigger detection on both the rising and falling edges"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Jqm",
            description: None,
            bit_size: 1,
            variants: &[
                EnumVariant {
                    name: "MODE0",
                    description: Some("JSQR Mode 0: Queue maintains the last written configuration into JSQR"),
                    value: 0,
                },
                EnumVariant {
                    name: "MODE1",
                    description: Some(
                        "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence",
                    ),
                    value: 1,
                },
            ],
        },
        Enum {
            name: "Res",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "BITS12",
                    description: Some("12-bit resolution"),
                    value: 0,
                },
                EnumVariant {
                    name: "BITS10",
                    description: Some("10-bit resolution"),
                    value: 1,
                },
                EnumVariant {
                    name: "BITS8",
                    description: Some("8-bit resolution"),
                    value: 2,
                },
                EnumVariant {
                    name: "BITS6",
                    description: Some("6-bit resolution"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "SampleTime",
            description: None,
            bit_size: 3,
            variants: &[
                EnumVariant {
                    name: "CYCLES1_5",
                    description: Some("1.5 ADC clock cycles"),
                    value: 0,
                },
                EnumVariant {
                    name: "CYCLES2_5",
                    description: Some("2.5 ADC clock cycles"),
                    value: 1,
                },
                EnumVariant {
                    name: "CYCLES4_5",
                    description: Some("4.5 ADC clock cycles"),
                    value: 2,
                },
                EnumVariant {
                    name: "CYCLES7_5",
                    description: Some("7.5 ADC clock cycles"),
                    value: 3,
                },
                EnumVariant {
                    name: "CYCLES19_5",
                    description: Some("19.5 ADC clock cycles"),
                    value: 4,
                },
                EnumVariant {
                    name: "CYCLES61_5",
                    description: Some("61.5 ADC clock cycles"),
                    value: 5,
                },
                EnumVariant {
                    name: "CYCLES181_5",
                    description: Some("181.5 ADC clock cycles"),
                    value: 6,
                },
                EnumVariant {
                    name: "CYCLES601_5",
                    description: Some("601.5 ADC clock cycles"),
                    value: 7,
                },
            ],
        },
    ],
};
